Senior Engineer (Level 2)

About the role

Position: Senior Engineer (Level 2) Job Description: Roles and Responsibilities:  ·       4 to 8 years of experience in SOC/IP/block level functional verification using System Verilog/UVM.   ·       Strong knowledge of UVM, advance UVM,System Verilog .   ·       Must have worked on development of testplan, testbench components, verification environment,…